F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

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ID 781679
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.3
IP Version 22.1.0

The F-Tile Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 provides the capability of generating design examples for selected configurations, which allows you to:

  • Compile the design to get an estimate of the IP area usage and timing.
  • Simulate the design to verify the IP functionality through simulation.
  • Test the design on the hardware using the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit.

When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Figure 1. Development Stages for the Design Example

Section Content
Directory Structure
Generating the Design Example
Simulating the F-Tile Triple-Speed Ethernet Intel FPGA IP Design Example Testbench
Compiling and Configuring the Design Example in Hardware

Level Two Title