I/O Expansion

To cost-effectively expand the I/O count of standard products, a high number of low-cost I/O pins becomes a key requirement for many system-level designs. The low-cost, flexible I/O capability of MAX® series devices are an ideal complement to today’s I/O pin-constrained ASSPs and microcontrollers. Table 1 describes some of the MAX II CPLD features that ease I/O expansion design challenges.

Table 1. MAX II CPLD Application Solutions: I/O Expansion

Features

Customer Benefits

Low Cost per I/O

Choose from a wide range of low cost MAX II CPLD package options and I/O counts.

Routing Flexibility

Freeze your PCB pin-out earlier knowing that Altera's design software can handle logic changes, using it's flexible interconnect routing resources, even with locked pin assignments.

Flexible I/O Banks

Multiple I/O banks support multiple I/O voltages, reducing the number of CPLDs per board.

Re-Programmability

PLDs offer the flexibility to make changes throughout the design cycle (prototype, production, or field upgrades), allowing OEMs to add new features at anytime.

Figure 1 shows how a MAX II CPLD can increase the effective I/O count of a microcontroller via a two-wire serial interface to control a larger number of peripheral devices. In this application example, the MAX II CPLD interfaces to the serial bus input and then distributes instructions to multiple fan motor controllers. Also, the MAX II CPLD‘s on-board user flash memory (UFM) can store information, such as the frequency or the duty cycle of the motors.

Data can also be converted from parallel to serial, such as taking information from the analog-to-digital converters (ADC) in parallel and communicating it to the microcontroller via the two-wire serial bus.

Figure 1. Expanding a Serial Bus Using MAX II CPLDs

Note:

  1. UFM: user flash memory

Many microprocessors are limited in I/O capability but need to distribute control signals to multiple devices around the system. Figure 2 shows how MAX II CPLDs can control a large number of devices on the board with only a minimal number of inputs from the host processor, thereby reducing I/O overhead support on the processor.

Figure 2. Control Signal Distribution Using MAX II CPLDs

Related Links

  • Link to Design Store