System Configuration and Initialization

MAX® series devices are commonly used to manage the configuration or initialization of a volatile device. Typical examples of components that require configuration or initialization include FPGAs, digital signal processors, ASSPs, and ASICs. Table 1 highlights MAX II device features and customer benefits.

Table 1. MAX II CPLD Application Solutions: System Configuration and Initialization

Features Customer Benefits
Non-Volatile and Instant-On Capability The CPLD is first to become functional and then configures or initializes the power-up sequence of the other devices on the board.
Real-Time ISP Reduces system downtime because you can download a new program into the MAX II on-board flash while its still operational. The new functionality becomes active immediately or at the next power-up scheduled by the user.
Parallel Flash Loader Megafunction This IP inside the MAX II devices allows discrete non-JTAG-compliant flash memory devices to be configured via the MAX II JTAG port while connected to the automatic test equipment or in the field. This application reduces programming time of the discrete flash devices.
User Flash Memory The MAX II device’s on-chip user flash memory might eliminate the need for smaller external flash memory devices.
Re-Programmability

PLDs offer the flexibility to make changes throughout the design cycle (prototype, production, or field upgrades), allowing OEMs to add new features at anytime.

Low Power CPLDs

Use low-power CPLDs to drive LCD's, buffer commands, etc. allowing higher powered ASSP's or ASICs to hibernate to achieve a lower overall system power.

MAX II CPLDs with the Parallel Flash Loader IP provide a one-chip solution for programming both discrete flash memories and configuring other devices (i.e. FPGAs) As shown in Figure 1, the initial step quickly programs the discrete flash device using JTAG via the MAX II device JTAG pins.

The second step uses discrete flash (where the FPGA configuration files are stored) and MAX II CPLD to configure multiple FPGAs. High densities MAX II CPLDs enable extremely complex configuration systems to be implemented, including having multiple pages within the discrete flash to program as many FPGAs as needed.

Figure 1. FPGA Configuration Management and Flash Controller Using a MAX II CPLD

Another system configuration application is shown in Figure 2. The FIFO configuration data is stored in the MAX II user flash memory, rather than in an external flash memory. The stored data can include information on the number of FIFO buffers, the number of data streams, and the almost empty/almost full offsets.

Figure 2. FIFO Configuration Management Using a MAX II CPLD