This is Volume 2 of the Datasheet for the Intel® Core™ i5-600, i3-500 Desktop processor series and Intel® Pentium® desktop processor 6000 series.
The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes these ...configuration space registers or device-specific control and status registers (CSRs) only. This document does NOT include Model Specific Registers (MSRs).
Throughout this document, the Intel® Core™ i5-600, i3-500 Desktop processor series and Intel® Pentium® desktop processor 6000 series may be referred to as “processor”.
Throughout this document, the Intel® 5 series Chipset Platform Controller Hub is also referred to as “PCH”.
System Address Map
The processor’s Multi Chip Package (MCP) conceptually consists of the processor and the north bridge chipset (GMCH) combined together in a single package. Hence, this section will have references to the processor as well as GMCH (or MCH) address mapping.
The MCP supports 64 GB (36 bit) of addressable memory space and 64 KB+3 of addressable I/O space. With the new QPI interface, the processor performs decoding that historically occurred within the GMCH. Specifically, the GMCH address decoding for processor initiated PAM, 15 MB–16 MB ISA hole, SMM CSEG/TSEG, PCIexBAR, and DRAM accesses will occur within the processor and the GMCH has no direct knowledge. In addition, the ME (device 3) will move to the PCH, so ME associated register ranges have been removed from the graphics controller. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has simpler mapping and is explained near the end of this section.
Read the full Intel® Core™/Pentium® Desktop Processor Series Datasheet, Vol. 2.