Heterogeneous 3D system-in-package integration.
Advances in 3D integration and packaging technologies now make it possible to build complex systems in single package comprised on multi-technology chiplets.
Historically, advanced integration used monolithic implementations due to power, performance, and cost considerations. With innovations in packaging and stacking technologies, designers can integrate their systems in a single package with chiplets that optimize specific functions using the process technology of choice.
Emerging system requirements demand very high interconnect bandwidth with minimal interface power/bit. Intel provides the two key elements to make this possible—ultra-short-reach interface standard and 3D integration packaging technology.
Standard Interface Enables Modular Design
Intel's Advanced Interface Bus (AIB) is a die-to-die PHY level standard that enables a modular approach to system design with a library of chiplet intellectual property (IP) blocks.
AIB uses a clock forwarded parallel data transfer mechanism similar to DDR DRAM interfaces. AIB is process and packaging technology agnostic—Intel's Embedded Multi-Die Interconnect Bridge (EMIB) or TSMC's CoWoS* for example.
Intel now provides the AIB interface license royalty-free to enable a broad ecosystem of chiplets, design methodologies or service providers, foundries, packaging, and system vendors.
Figure: example of a possible heterogeneous system in package (SiP) that combines sensors, proprietary ASIC, FPGA, CPU, Memory, and I/O using AIB as the chiplet interface.
Download this white paper to learn more about how Intel® Stratix® 10 FPGAs and SoCs leverage heterogeneous 3D SiP integration to deliver performance, power, and form factor breakthroughs while providing greater scalability and flexibility. In addition, learn how Intel EMIB technology delivers a superior solution for multi-die integration.