VHDL Templates for State Machines v1.0 README File This readme file for the VHDL Templates for State Machines contains information about the design example in the Quartus ll HDL Templates. Ensure that you have read the information on the VHDL Templates for State Machines Design Example web page before using the example. The VHDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine This file contains the following information: o Package Contents o Software Tool Requirements o Release History o Technical Support Package Contents ================ Each zip download includes the VHDL file and the top level block diagram for each of the following state machines: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine Software Tool Requirements ========================== The Quartus II software version 9.1 or later, or supported versions of third-party synthesis tools. Contact your local sales representative if you do not have the necessary software tools. Release History =============== Version 1.0 ----------- - First release of example. Technical Support ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, refer to the Altera technical support web site: http://www.altera.com/mysupport Last updated May, 2010 Copyright (c) 2010 Altera Corporation. All rights reserved.