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IA-PC High Precision Event Timers: Specification

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IA-PC High Precision Event Timers: Specification

1.2 Scope
This specification provides register model and programming interface definitions for new event timer hardware for use on Intel Architecture-based personal computers. In this specification, the terms IA-PC HPET and Event Timers refer to the same timer hardware.

The IA-PC HPET specification defines timer hardware that is intended to initially supplement and eventually replace the legacy 8254 Programmable Interval Timer and the Real Time Clock Periodic Interrupt generation functions that are currently used as the ‘de-facto’ timer hardware for IA-PCs. This new timer hardware can be used by system software for:
• Synchronizing
• Real-Time Digital Audio & Video Streams: 64-bit free running up-counter

Scheduling
• Threads, Tasks, Processes, etc.: Fixed Rate (Periodic) Interrupt Generation - • System Heart Beat
• Non-Real Time Thread Scheduler

Variable Rate (One-Shot) Interrupt Generation: • Scheduling real time tasks associated with host-based signal processing applications

Time Stamping
1. On Multiprocessor platforms: 64-Bit free running up-counter can be utilized as DIG64 “platform timer” for Time Stamping Applications. This provides a time-base that is insensitive to clock frequency drifts on individual CPU’s on a N-Way MP systems.

2. Hardware overview
The IA-PC HPET architecture defines a set of timers that can be used by the operating system. The timers are defined such that in the future, the OS may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to generate a separate interrupt. This specification allows for a block of 32 timers, with support for up to 8 blocks, for a total of 256 timers. However, specific implementations can include only a subset of these timers. The timers are implemented as a single up-counter with a set of comparators. The counter increases monotonically. When software does two consecutive reads of the counter, the second read will never return a value that is less than the first read unless the counter has actually rolled over. Each timer includes a match register and a comparator. Each individual timer can generate an interrupt when the value in its match register equals the value of the free-running counter. Some of the timers can be enabled to generate a periodic interrupt.

Read the full IA-PC High Precision Event Timers specification.