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Microarquitectura Intel® basada en 32 nm

La nueva microarquitectura Intel® combina integración y fabricación de procesadores en la 2ª generación de la familia de procesadores Intel® Core™.

Platform-Level Error Handling Strategies for Intel® Systems

White Paper: Provides platform-level error handling strategies and overview of error detection and notification capabilities. (v.001, May 2011)

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Reduce Interrupt Latency in Embedded Systems

White Paper: MSI remove limitations associated with Intel® architecture, reduce interrupt latency and overhead, improving performance. (Jan. 2009)

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JTAG 101: IEE 1149.x and Software Debug

White Paper: Quick JTAG 101 overview of the various implementations and names of debug methods to help users migrate to IA32. (Jan. 2009)

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Embedded Intel® Architecture and High Speed Digital Design

White Paper: Board behavior of high speed digital signals and available design tools for embedded Intel® architecture products. (Jan. 2009)

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Migration Solutions for Embedded Intel® Architecture

Klocwork* analyzes source code and inspects codebase before Intel® architecture migration, minimizing cost, effort, and complexity. (v.001, Oct. 2011)

Basics of Building Intel® Architecture Design

White Paper: Describes elements of Intel® architecture design, including voltage regulators, clock sources, and power sequencing. (v.1, Sept. 2010)

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Debugging Processor Reorder Buffer Timeout: Guide

Guide: Describes processor reorder buffer timeout and provides methodology for debugging these types of system issues. (v.1, Oct. 2010)

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