• <Más en Intel.com

Intel® 82577 GbE PHY: Datasheet

Lo sentimos, este PDF sólo está disponible en formato para descarga

Intel® 82577 GbE PHY: Datasheet

Scope

This document describes the external architecture for the Intel® 82577 Gigabit Ethernet PHY. It is intended to be a reference for software developers of device drivers, board designers, test engineers, or anyone else who might need specific technical or programming information about the 82577.

Overview

The 82577 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Intel® 5 Series Express Chipset integrated Media Access Controller (MAC) through a dedicated interconnect. The 82577 supports operation at 1000/100/10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab).

The 82577 is packaged in a small footprint QFN package. Package size is 6 x 6 mm with a 0.4 mm lead pitch and a height of 0.85 mm, making it very attractive for small form-factor platforms.

The 82577 interfaces with its MAC through two interfaces: PCIe-based and SMBus. The PCIe (main) interface is used for all link speeds when the system is in an active state (S0) while the SMBus is used only when the system is in a low power state (Sx). In SMBus mode, the link speed is reduced to 10 Mb/s (dependent on low power options). The PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic protocol.

Note: The 82577 PCIe interface is not PCIe compliant. It operates at half of the PCI Express* (PCIe*) Specification v1.1 (2.5 GT/s) speed. In this datasheet the term PCIe-based is interchangeable with PCIe. There is no design layout differences between normal PCIe and the 82577’s PCIe-based interface.

Read the full Intel® 82577 GbE PHY Datasheet